Integrated decoupling capacitors

ABSTRACT

A method for fabricating buried decoupling capacitors in an integrated circuit is disclosed. The method forms decoupling capacitors by creating an opening within a substrate which has fin-like spacers, depositing a dielectric material over the spacers, depositing an electrode material over the dielectric material, depositing an insulative material over the electrode material, and forming integrated circuit components over the insulative material.

FIELD OF THE INVENTION

[0001] The present invention relates to the field of integrated circuitsand, in particular, to a method of fabricating compact decouplingcapacitors within integrated circuits.

BACKGROUND OF THE INVENTION

[0002] Integrated circuits, particularly those used in computer systems,continuously become more powerful and operate at faster speeds. Tosupply power to-circuit components, metal layers dedicated to powersupply distribution are formed in the circuits in order to maintain alow inductive voltage drop. The inductive voltage drop can neverthelessbe substantial, causing high frequency noise that is superimposed uponthe power supply voltage. For future generations of components withmulti-GHz chips, in particular, noise in the power and ground linesincreasingly becomes a problem.

[0003] Bypass capacitors or decoupling capacitors, which act as a chargereservoir, provide an effective way to suppress the power distributionnoise. Additionally, decoupling capacitors provide better electricalperformance of the integrated circuit. As a result of these benefits,decoupling capacitors are used in many circuit designs.

[0004] Decoupling capacitors have been formed over underlying circuitryand/or device layers. For example, with reference to FIG. 1, circuits 10have been formed having a substrate 2 and device containing layer 4.Thereafter, a decoupling capacitor is formed by deposing dielectriclayers 6, 8, and 11, and conductive layers 7 and 9, wherein combinedlayers indicated by numeral 13 form a decoupling capacitor. Asillustrated in FIG. 2, the capacitor plate(s) can be connected to theunderlying components, or a power source, by forming a connective layer15 which extends between a capacitor plate 9 and an underlyingconductive layer 4. Insulating surfaces 17 are provided to preventelectrical shorts between conductive layers 7 and 9.

[0005] The existing methods for fabricating decoupling capacitors,however, fall short of increasing industry demands that require newperformance criteria from supporting components, such as better locationwithin the integrated circuit and higher performance parameters inhigh-speed environments. What is needed is a method of fabricatingdecoupling capacitors that are compact, have high-performancecharacteristics, and are located strategically within the integratedcircuit to decouple transient noise and other undesirable signals.

SUMMARY OF THE INVENTION

[0006] The present invention discloses a method of fabricating compactdecoupling capacitors that are buried in a substrate, and are locatedstrategically to decouple transient noise and other undesirable signals.

[0007] A method of forming decoupling capacitors for reducingundesirable noise in an integrated circuit is disclosed, comprisingforming an opening within a substrate, where the opening containsfin-like spacers, depositing a dielectric material over the spacers,depositing an electrode material over the dielectric material,depositing an insulative material over the electrode material, andforming integrated circuit components over the insulative material.

[0008] Additional features and advantages of the present invention willbe more clearly apparent from the detailed description which is providedin connection with accompanying drawings which illustrate exemplaryembodiments of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009]FIG. 1 is a side-sectional view of a prior art integrated circuitcontaining a decoupling capacitor;

[0010]FIG. 2 is a view of the integrated circuit of FIG. 1 at asubsequent stage of fabrication;

[0011]FIG. 3 is a perspective view of a integrated circuit substrate inaccordance with an embodiment of the present invention;

[0012]FIG. 4 is a cross-sectional view taken along lines IV-IV of theintegrated circuit substrate of FIG. 3.

[0013]FIG. 5A is an exploded view of the fin-like structures of FIG. 4.

[0014]FIG. 5B is a view of the fin-like structures of FIG. 5A at asubsequent stage of fabrication.

[0015]FIG. 5C is a view of the fin-like structures of FIG. 5B at asubsequent stage of fabrication.

[0016]FIG. 6 is a perspective view of the integrated circuit substrateof FIG. 4 at a subsequent stage of fabrication.

[0017]FIG. 6A is a top view of the integrated circuit substrate of FIG.6.

[0018]FIG. 7 is a view of the integrated circuit substrate of FIG. 4 ata subsequent stage of fabrication.

[0019]FIG. 7A is a top view of the integrated circuit substrate of FIG.7.

[0020]FIG. 8 is a side sectional view of an integrated circuit substratein accordance with another embodiment of the present invention.

[0021]FIG. 9 is a side view of the integrated circuit substrate of FIG.8.

[0022]FIG. 10 is a view of the integrated circuit substrate if FIG. 8 ata subsequent stage of application.

[0023]FIG. 11 is a top view of the integrated circuit substrate of FIGS.6 and/or 7 at a subsequent stage of fabrication.

[0024]FIG. 12 is a side sectional view of the integrated circuitsubstrate of FIG. 11.

[0025]FIG. 13 is a side sectional view of the integrated circuitsubstrate of FIG. 12 at a subsequent stage of fabrication.

[0026]FIG. 14 is a side sectional view of the integrated circuitsubstrate of FIG. 13 at a subsequent stage of fabrication.

[0027]FIG. 15 is a top view of the integrated circuit substrate of FIG.14.

[0028]FIG. 16 is a side sectional view of the integrated circuitsubstrate of FIG. 14 at a subsequent stage of fabrication.

[0029]FIG. 17 is a top view of an integrated circuit substrate inaccordance with an embodiment of the present invention.

[0030]FIG. 18 is a side sectional view of a fin-like structure andcovering material layers in accordance with another embodiment of thepresent invention.

[0031]FIG. 19 is a diagram of a computer system according to anembodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0032] In the following detailed description, reference is made tovarious specific embodiments in which the invention may be practiced.These embodiments are described with sufficient detail to enable thoseskilled in the art to practice the invention, and it is to be understoodthat other embodiments may be employed, and that structural andelectrical changes may be made without departing from the spirit orscope of the present invention.

[0033] The term “substrate” used in the following description mayinclude any semiconductor-based structure that has a semiconductorsurface. The term should be understood to include silicon,silicon-on-insulator (SOI), silicon-on-sapphire (SOS),silicon-on-nothing (SON), doped semiconductors, epitaxial layers ofsilicon supported by a base semiconductor foundation, and othersemiconductor structures. The semiconductor need not be silicon-based.The semiconductor could be silicon-germanium, germanium, or galliumarsenide. When reference is made to a “substrate” in the followingdescription, previous process steps may have been utilized to formregions or junctions in or on the base semiconductor or foundation.

[0034] Referring now to the drawings, where like elements are designatedby like reference numerals, FIG. 3 depicts a portion of a substrate 30which is formed by methods well known in the art. Preferably, thesubstrate 30 comprises a heavily doped silicon. The substrate 30 can bedoped using Alcatel-Mietec's deep n-dope+drive process, or anothersuitable process. In the substrate 30 a microstructure 40 of siliconfins is fabricated utilizing deep anisotropic plasma etching, such ashigh etch rate bulk silicon etching. An exemplary deep plasma etchingtechnique that can be utilized in the present invention is thatdisclosed by Tam Pandhumsoporn, et al., “High etch rate, deepanisotropic plasma etching of silicon for MEMS fabrication,” SPIE Vol.3328, March 1998. As a result of the high etch rate bulk siliconetching, the fan-like structure 40 is formed in the silicon substrate30. A helpful illustration of the structure 40 is provided in FIG. 4,that depicts a cross-sectional view along line IV-IV of FIG. 3. FIG. 4illustrates multiple fins or supports 50 formed in a fan-like patternabout a center of the circular opening of structure 40. The structure 40need not be circular and may, for example, be oval in shape.

[0035] The resulting structure 40 is comprised of trenches or openspaces 45 that define a series of fins or supports 50. Each fin 50 is amicrostructure that will ultimately become a capacitor, as will bedisclosed herein, so the number of fins 50 etched in the structure 40will depend on multiple integrated circuit design goals and limitations.A structure 40 having a minimum of ten (10) fins 50 is recommended. Thefins 50 formed by the above disclosed method have a thickness ofapproximately 30 microns, however, the thickness can be increased ordecreased by the practitioner.

[0036] With reference to FIGS. 5A-C, formation of the capacitors inaccordance with the present invention will be described. FIG. 5Aillustrates three of the several fins 50 in the substrate 30 viewed froma perspective similar to that of FIG. 4. Unfilled spaces 45 are between,and define the fins 50. The fins 50 comprise the bottom electrode, orcell plate, of the resulting capacitor. Next, with reference to FIG. 5B,a layer of dielectric material 55 is deposited over the fins 50 andsubstrate 30 utilizing a process such as Chemical Vapor Deposition (CVD)for conformal coating of the underlying layers. Another exemplarytechnique for depositing layer 55 is by low temperature Metal OrganicChemical Vapor Deposition (MOCVD) utilizing (BaSr)TiO₃ films. The MOCVDdeposition of BST or BSTO films as a dielectric provides for additionalbenefits such as conformal coverage of underlying layers and preventionof oxidation. Because the present invention endeavors to form capacitorshaving high capacitance, it is preferable that the dielectric materialhave a high dielectric constant, such as 50 or greater, and a thicknessof less than 1000 Angstroms. However, the dielectric layer 55 cancomprise various materials with a lower dielectric constant and/orhaving a higher thickness without departing from the scope of thepresent invention, as comparable changes will affect only the electricalcharacteristics of the resulting capacitor.

[0037] Thereafter, with reference to FIG. 5C, a top electrode layer 57is deposited over the dielectric layer 55. The top electrode layer 57 ispreferably a metallic film of a noble metal such platinum. The topelectrode layer 57 may have a thickness of less than one (1) micron,however, other thicknesses and materials may be used. The unfilledspaces 45A between adjacent structures comprising layers 50, 55, and 57are reduced as compared to unfilled spaces 45 of FIGS. 5A and 5B.

[0038] A perspective view of the resulting structure 40, afterdeposition of layers 55 and 57, is shown in FIGS. 6 and 6A. Thesubstrate 30 is connected to fins 50, not visible in FIGS. 6 and 6A, andfunctions as the ground plate of the resulting capacitor(s). Thedielectric layer 55 separates both the substrate 30 and the fins 50 fromthe top electrode layer 57. The unfilled spaces 45A separate eachindividual structure comprising the fin 50, dielectric 55, and topelectrode 57. An alternative resulting structure 40 is illustrated inFIGS. 7 and 7A. Therein, unfilled spaces 45B extend toward the center ofthe structure 40. The size and shape of the unfilled spaces 45A and 45Bwill depend, among other factors, on the number of fins 50 etched intothe substrate 30, and the thickness of the fins 50 and the layers 55 and57. The structure 40 is completed by depositing into the unfilled spaces45A or 45B an insulating material.

[0039] In another embodiment of the present invention, illustrated inFIGS. 8 and 9, the fins 50 are etched, in accordance with techniquesdescribed above, to be separated from the interior wall 43 of structure40. This structure, in addition to openings 45 between individual fins50, has an opening 45C between the fins 50 and the interior wall 43 ofsubstrate 30. Thereafter, utilizing techniques described above,dielectric layer 55 and top electrode layer 57 are deposited over thefins 50, as shown in FIG. 10. The resulting structure 40 of thisembodiment allows for each fin 50, with layers 55 and 57, to function asan individual capacitor.

[0040] Next, with reference to FIGS. 11 and 12, the top of the structure40 and substrate 30 is sealed with an insulative layer 60. An exemplarymaterial for layer 60 is photo-definable polyimide, such as PT 412manufactured by Ciba-Geigy Corporation, that is spin-coated onto thesurfaces. Alternatively, the insulative layer 60 material can be anotherinsulator. The deposition of the insulative layer, and the deposition ofan insulative material into spaces 45A, 45B, and 45C as described above,can be accomplished in one process step. Alternatively, the insulativelayer 60 can be deposited to cover only the structure 40.

[0041] The top surface 41 of structure 40 in FIG. 12, and in subsequentFigures showing a similar side-sectional view, is shown as extendingabove the top surface 31 of substrate 30. This represents the addedthickness of layers 55 and 57, deposited over the fins 50, if the topsurfaces of the fins 50 and substrate 30 are elevationally similar, asshown in FIG. 4. The top surface 41 of the structure 40 can be madeelevationally similar to or lower than the top surface 31 of substrate30 by etching the top surfaces of fins 50 to be lower than the topsurface 31 of substrate 30 during process steps previously described.

[0042] To form electrical contact opening(s) in the structure 40, alayer of photoresist 63 is formed over the insulating layer 60 to defineopenings 65, as shown in FIG. 13. Thereafter, openings 67 are etchedthrough the insulative layer 60 down to the top electrode layer 57, andthe photoresist layer 63 is subsequently removed, as shown in FIG. 14.An illustrative top view of the openings 67 is shown in FIG. 15. Theopening 67C would be formed if the center of the structure 40 is filledwith the top electrode layer 57 in the process steps mentioned above.The quantity and locations of openings 67 to the top electrode layer 57will be chosen by the practitioner according to the number and/orplacement of electrical connections desired in the resulting integratedcircuit. If the structure 40 is formed in accordance with the embodimentshown in FIGS. 8, 9, and 10, openings 67 would be created over eachindividual capacitor structure.

[0043] An example of a circuit made possible by the present invention isshown in FIG. 16, wherein an electrical via 80 connects the capacitorstructure 40 with a voltage line, or a power supply interconnectinglayer 75. The layer 75 may, in turn, supply electrical power to a powerlayer 77 and various other components. In FIG. 16, layers 70 and 73 canbe insulating layers, or layers containing different integrated circuitcomponents, and the via 80 is electrically isolated from those layers.

[0044] The number of capacitor structures 40 can be chosen by thepractitioner to accommodate the desired integrated circuit, asillustrated in FIG. 17 that shows a substrate 30 with multiple capacitorstructures 40.

[0045] In another embodiment of the present invention, illustrated inFIG. 18, the fins of structure 40 may be formed to have a larger surfaceon the top 91 of the fin 90, resembling a “T” shape. Such structures maybe achieved by undercutting and profiling utilizing the high etch ratebulk silicon etching process discussed above. These fins 90 offer thebenefit of providing a greater surface area for the resulting capacitorstructure, thus enabling a higher resulting capacitance than fins 50that are uniform in thickness. The fin 90 would then be covered with adielectric layer 93 and a top electrode layer 95 to complete thecapacitor structure. Alternatively, the fins 90 can be undercut andprofiled to have a variable thickness, increasing from bottom to top orvice versa.

[0046]FIG. 19 illustrates a computer system 300 that may incorporate thebenefits of the present invention. The system 300 has a memory circuit321 coupled through bus 310 to a central processing unit (CPU) 302 forperforming computer functions, such as executing software to perform 5desired tasks and calculations. One or more of the memory circuits 321and CPU 302 may capacitors constructed in accordance with the presentinvention. One or more input/output devices 304, 306, such as a keypador a mouse, are coupled to the CPU 302 and allow an operator to manuallyinput data thereto or to display or otherwise output data generated bythe 10 CPU 302. One or more peripheral devices such as a floppy diskdrive 312 or a CD ROM drive 314 may also be coupled to the CPU 302. Thecomputer system 300 also includes a bus 310 that couples theinput/output devices 312, 314 and the memory circuit 321 to the CPU 302.

[0047] While exemplary embodiments of the invention have been described1i and illustrated, it should be apparent that many modifications can bemade to the present inventions without departing from their spirit andscope. Accordingly, the invention is not limited by the foregoingdescription or drawings, but is only limited by the scope of theappended claims.

What is claimed as new and desired to be protected by Letters Patent ofthe United States is:
 1. A method of forming a capacitor structurecomprising: forming an opening in a doped semiconductor substrate whichcontains fin-like spacers extending from a bottom surface of saidopening and formed of a doped semiconductor material; forming adielectric material layer over the spacers; and forming an electrodematerial layer over the dielectric material.
 2. The method according toclaim 1 wherein said opening is formed to be a circular opening.
 3. Themethod according to claim 2 wherein said fin-like spacers are formed ina fan-like pattern about a center of said circular opening.
 4. Themethod according to claim 1 further comprising forming an insulatingmaterial layer over said electrode material.
 5. The method according toclaim 4 further comprising forming contact openings in said insulatingmaterial.
 6. The method according to claim 5 wherein said contactopenings are formed over at least one of said fin-like spacers.
 7. Themethod according to claim 5 wherein said contact openings are formedover a center of said opening in said substrate.
 8. The method accordingto claim 4 further comprising forming integrated circuit components oversaid insulating layer.
 9. The method according to claim 5 furthercomprising forming a conductive via through said contact openings, andconnecting said conductive via to a voltage line.
 10. The methodaccording to claim 1 wherein said fin-like spacers and bottom of theopening form a lower plate of said capacitor.
 11. The method accordingto claim 10 wherein said lower plate forms a ground plate of saidcapacitor.
 12. The method according to claim 1 wherein each saiddielectric and electrode material layers are formed over said fin-likespacers to provide a plurality of capacitors.
 13. The method accordingto claim 1 wherein said dielectric and electrode material layers areformed over said fin-like spacers to provide a single capacitor.
 14. Themethod according to claim 4 wherein said insulative material layercomprises a photo-definable polyimide layer.
 15. The method according toclaim 1 wherein said dielectric material layer comprises a BST layer.16. The method according to claim 1 wherein said dielectric materiallayer comprises a BSTO layer.
 17. The method according to claim 1wherein said dielectric material layer is formed by MOCVD.
 18. Themethod according to claim 1 wherein said dielectric material layer isformed by CVD.
 19. The method according to claim 1 wherein saidelectrode material layer comprises a noble metal layer.
 20. The methodaccording to claim 1 wherein said fin-like spacers are formed to have aconstant thickness in cross-section.
 21. The method according to claim 1wherein said fin-like spacers are formed to have a “T” shapedcross-section.
 22. The method according to claim 1 wherein said fin-likespacers are formed to have one of an increasing and decreasingcross-section.
 23. The method according to claim 1 wherein saiddielectric material layer comprises a material having a dielectricconstant of at least
 50. 24. A method of forming a capacitor in anintegrated circuit comprising: forming an opening in a dopedsemiconductor substrate which contains supports of a doped semiconductormaterial; forming a dielectric material layer over said supports;forming an electrode material layer over said dielectric material; saidcapacitor being a decoupling capacitor within said integrated circuit.25. The method according to claim 24 wherein said opening is formed tobe a circular opening.
 26. The method according to claim 25 wherein saidsupports are formed in a fan-like pattern about a center of saidcircular opening.
 27. The method according to claim 24 furthercomprising forming an insulating material layer over said electrodematerial.
 28. The method according to claim 27 further comprisingforming contact openings in said insulating material.
 29. The methodaccording to claim 28 wherein said contact openings are formed over atleast one of supports.
 30. The method according to claim 28 wherein saidcontact openings are formed over a center of said opening in saidsubstrate.
 31. The method according to claim 27 further comprisingforming integrated circuit components over said insulating layer. 32.The method according to claim 28 further comprising forming a conductivevia through said contact openings, and connecting said conductive via toa voltage line.
 33. The method according to claim 24 wherein saidsupports and bottom of the opening form a lower plate of the capacitor.34. The method according to claim 33 wherein said lower plate forms aground plate of said capacitor.
 35. The method according to claim 27wherein said insulating material layer comprises a photo-definablepolyimide layer.
 36. The method according to claim 24 wherein saiddielectric material layer comprises a BST layer.
 37. The methodaccording to claim 24 wherein said dielectric material layer comprises aBSTO layer.
 38. The method according to claim 24 wherein said dielectricmaterial layer is formed by MOCVD.
 39. The method according to claim 24wherein said dielectric material layer is formed by CVD.
 40. The methodaccording to claim 24 wherein said electrode material layer comprises anoble metal layer.
 41. The method according to claim 24 wherein saidsupports have a constant thickness in cross-section.
 42. The methodaccording to claim 24 wherein said supports have a “T” shapedcross-section.
 43. The method according to claim 24 wherein saidsupports have one of increasing and decreasing cross-section.
 44. Themethod according to claim 24 wherein said dielectric material layercomprises a material having a dielectric constant of at least
 50. 45.The method according to claim 24 wherein each said dielectric andelectrode material layers are formed over said supports to provide aplurality of capacitors.
 46. The method according to claim 24 whereinsaid dielectric and electrode material layers are formed over saidsupports to provide a single capacitor.
 47. A method of fabricating acapacitor in an integrated circuit comprising: forming an opening withina doped semiconductor substrate, said substrate opening containingmicrostructures formed of a doped semiconductor material; forming adielectric material over said microstructures; forming an electrodematerial over said dielectric material; and forming integrated circuitcomponents over said insulative material.
 48. The method according toclaim 47 wherein said opening is formed to be a circular opening. 49.The method according to claim 48 wherein said microstructures are formedin a fan-like pattern about a center of said circular opening.
 50. Themethod according to claim 47 further comprising forming an insulatingmaterial over said electrode material.
 51. The method according to claim50 further comprising forming contact openings in said insulatingmaterial.
 52. The method according to claim 51 wherein said contactopenings are formed over at least one of said microstructures.
 53. Themethod according to claim 51 wherein said contact openings are formedover a center of said opening in said substrate.
 54. The methodaccording to claim 51 further comprising forming a conductive viathrough said contact openings, and connecting said conductive via tovoltage line.
 55. The method according to claim 47 wherein saidcapacitor has the function of a decoupling capacitor.
 56. The methodaccording to claim 47 wherein said microstructures and bottom of theopening form a lower plate of the capacitor.
 57. The method according toclaim 56 wherein said lower plate forms a ground plate of saidcapacitor.
 58. The method according to claim 50 wherein said insulatingmaterial comprises a photo-definable polyimide material.
 59. The methodaccording to claim 47 wherein said dielectric material comprises a BSTmaterial.
 60. The method according to claim 47 wherein said dielectricmaterial comprises a BSTO material.
 61. The method according to claim 47wherein said dielectric material is formed by MOCVD.
 62. The methodaccording to claim 47 wherein said dielectric material is formed by CVD.63. The method according to claim 47 wherein said electrode materialcomprises a noble metal material.
 64. The method according to claim 47wherein said microstructures are formed to have a constant thickness incross-section.
 65. The method according to claim 47 wherein saidmicrostructures are formed to have a “T” shaped cross-section.
 66. Themethod according to claim 47 wherein said microstructures are formed tohave one of increasing and decreasing cross-section.
 67. The methodaccording to claim 47 wherein said dielectric material comprises amaterial having a dielectric constant of at least
 50. 68. The methodaccording to claim 47 wherein each said dielectric and electrodematerial layers are formed over said microstructures to provide aplurality of capacitors.
 69. The method according to claim 47 whereinsaid dielectric and electrode material layers are formed over saidmicrostructures to provide a single capacitor.
 70. A method of reducingnoise in an integrated circuit comprising: providing a dopedsemiconductor substrate; forming a capacitor that is recessed withinsaid substrate, forming semiconductor components over said substrate,said components including a voltage line; and forming an electricalconnection between said capacitor and said voltage line.
 71. The methodaccording to claim 70 wherein said capacitor functions as a decouplingcapacitor.
 72. The method according to claim 70 wherein forming saidcapacitor further includes forming an opening within said substrate. 73.The method according to claim 72 wherein said opening is formed to be acircular opening.
 74. The method according to claim 73 further includingforming microstructures within said opening.
 75. The method according toclaim 74 wherein said microstructures are formed in a fan-like patternabout a center of said opening.
 76. The method according to claim 74wherein said microstructures and bottom of said opening form a lowerplate of said capacitor.
 77. The method according to claim 76 whereinsaid lower plate forms a ground plate of said capacitor.
 78. The methodaccording to claim 74 further comprising forming a dielectric materiallayer over said microstructures.
 79. The method according to claim 76further comprising forming an electrode material layer over saiddielectric material layer.
 80. The method according to claim 79 furthercomprising forming an insulating material layer over said electrodematerial layer.
 81. The method according to claim 80 further comprisingforming contact openings in said insulating material layer.
 82. Themethod according to claim 81 wherein said contact openings are formedover at least one of said microstructures.
 83. The method according toclaim 81 wherein said contact openings are formed over a center of saidopening in said substrate.
 84. The method according to claim 79 whereineach said dielectric and electrode material layers are formed over saidmicrostructures to provide a plurality of capacitors.
 85. The methodaccording to claim 79 wherein said dielectric and electrode materiallayers are formed over said microstructures to provide a singlecapacitor.
 86. The method according to claim 80 wherein said insulatingmaterial layer comprises a photo-definable polyimide layer.
 87. Themethod according to claim 78 wherein said dielectric material layercomprises a BST material layer.
 88. The method according to claim 78wherein said dielectric material layer comprises a BSTO material layer.89. The method according to claim 78 wherein said dielectric materiallayer is formed by MOCVD.
 90. The method according to claim 78 whereinsaid dielectric material layer is formed by CVD.
 91. The methodaccording to claim 79 wherein said electrode material layer comprises anoble metal layer.
 92. The method according to claim 74 wherein saidmicrostructures are formed to have a constant thickness incross-section.
 93. The method according to claim 74 wherein saidmicrostructures are formed to have a “T” shaped cross-section.
 94. Themethod according to claim 74 wherein said microstructures are formed tohave one of an increasing and decreasing cross-section.
 95. The methodaccording to claim 78 wherein said dielectric material layer comprises amaterial having a dielectric constant of at least
 50. 96. An integratedcircuit comprising: a doped semiconductor substrate having an openingtherein containing fin-like spacers formed of a doped semiconductormaterial; a dielectric material formed over said spacers; an electrodematerial formed over said dielectric material; and an insulatingmaterial formed over said electrode material.
 97. The circuit accordingto claim 96 wherein said opening is a circular opening.
 98. The circuitaccording to claim 97 wherein said fin-like spacers are in a fan-likepattern about a center of said circular opening.
 99. The circuitaccording to claim 96 further comprising integrated circuit componentsformed over said insulating material.
 100. The circuit according toclaim 99 further comprising forming contact openings in said insulatingmaterial.
 101. The method according to claim 100 wherein said contactopenings are formed over at least one of said fin-like spacers.
 102. Themethod according to claim 100 wherein said contact openings are formedover a center of said opening in said substrate.
 103. The circuitaccording to claim 81 further comprising forming a conductive viathrough said contact openings, said conductive via being connected to avoltage line.
 104. The circuit according to claim 96 wherein saidfin-like spacers and bottom of said opening form a lower plate of saidcapacitor.
 105. The circuit according to claim 104 wherein said lowerplate forms a ground plate of said capacitor.
 106. The circuit accordingto claim 96 wherein said insulating material comprises a photo-definablepolyimide layer.
 107. The circuit according to claim 96 wherein saiddielectric material comprises a BST layer.
 108. The circuit according toclaim 96 wherein said dielectric material comprises a BSTO layer. 109.The circuit according to claim 96 wherein said dielectric material isformed by MOCVD.
 110. The circuit according to claim 96 wherein saiddielectric material is formed by CVD.
 111. The circuit according toclaim 96 wherein said electrode material comprises a noble metal layer.112. The circuit according to claim 96 wherein said fin-like spacershave a constant thickness in cross-section.
 113. The circuit accordingto claim 96 wherein said fin-like spacers have a “T” shapedcross-section.
 114. The circuit according to claim 96 wherein saidfin-like spacers have one of increasing and decreasing cross-section.115. The circuit according to claim 96 wherein said dielectric layercomprises a material having a dielectric constant of at least
 50. 116.The method according to claim 96 wherein each said dielectric andelectrode material layers are formed over said fin-like spacers toprovide a plurality of capacitors.
 117. The method according to claim 96wherein said dielectric and electrode material layers are formed oversaid fin-like spacers to provide a single capacitor.
 118. A computersystem comprising: a processor; and a memory device coupled to saidprocessor, at least one of said processor and memory device containing acapacitor comprising: a substrate having an opening therein containingfin-like spacers formed of a doped semi-conductor material, a dielectricmaterial formed over said spacers, and an electrode material formed oversaid dielectric material.
 119. The system according to claim 118 whereinsaid opening is a circular opening.
 120. The system according to claim119 wherein said fin-like spacers are formed in a fan-like pattern abouta center of said circular opening.
 121. The system according to claim118 further comprising an insulating material over said electrodematerial.
 122. The system according to claim 121 further comprisingforming contact openings in said insulating material.
 123. The methodaccording to claim 122 wherein said contact openings are formed over atleast one of said fin-like spacers.
 124. The method according to claim122 wherein said contact openings are formed over a center of saidopening in said substrate.
 125. The system according to claim 121further comprising integrated circuit components over said insulatingmaterial.
 126. The system according to claim 122 further comprising aconductive via formed through said contact openings, said conductive viaconnecting to a voltage line.
 127. The system according to claim 118wherein said fin-like spacers and bottom of said opening form a lowerplate of the capacitor.
 128. The system according to claim 118 whereinsaid lower plate forms a ground plate of capacitor.
 129. The systemaccording to claim 121 wherein said insulative material comprises aphoto-definable polyimide material.
 130. The system according to claim118 wherein said dielectric material comprises a BST material.
 131. Thesystem according to claim 118 wherein said dielectric material comprisesa BSTO material.
 132. The system according to claim 118 wherein saiddielectric material is formed by MOCVD.
 133. The system according toclaim 118 wherein said dielectric material is formed by CVD.
 134. Thesystem according to claim 118 wherein said electrode material comprisesa noble metal material.
 135. The system according to claim 118 whereinsaid fin-like spacers have a constant thickness in cross-section. 136.The system according to claim 118 wherein said fin-like spacers have a“T” shaped cross-section.
 137. The system according to claim 118 whereinsaid fin-like spacers have one of increasing and decreasingcross-section.
 138. The system according to claim 118 wherein saiddielectric material comprises a material having a dielectric constant ofat least
 50. 139. The method according to claim 118 wherein each saiddielectric and electrode material layers are formed over said fin-likespacers to provide a plurality of capacitors.
 140. The method accordingto claim 118 wherein said dielectric and electrode material layers areformed over said fin-like spacers to provide a single capacitor.
 141. Acapacitor structure comprising: a doped semiconductor substrate having acircular opening therein; doped semiconductor microstructures formed ina fan-like pattern about a center of said circular opening; a dielectricmaterial over said microstructures; and an electrode material over saiddielectric material.
 142. The structure according to claim 141 furthercomprising an insulating material over said electrode material.
 143. Thestructure according to claim 142 further comprising contact openings insaid insulating material.
 144. The method according to claim 143 whereinsaid contact openings are formed over at least one of saidmicrostructures.
 145. The method according to claim 143 wherein saidcontact openings are formed over said center of said opening in saidsubstrate.
 146. The structure according to claim 142 further comprisingintegrated circuit components over said insulating material.
 147. Thestructure according to claim 143 further comprising a conductive viaformed through said contact openings, said conductive via connected to avoltage line.
 148. The structure according to claim 141 wherein saidmicrostructures and bottom of said opening form a lower plate of thecapacitor.
 149. The structure according to claim 148 wherein said lowerplate forms a ground plate of capacitor.
 150. The structure according toclaim 142 wherein said insulating material comprises a photo-definablepolyimide material.
 151. The structure according to claim 141 whereinsaid dielectric material comprises a BST material.
 152. The structureaccording to claim 141 wherein said dielectric material comprises a BSTOmaterial.
 153. The structure according to claim 141 wherein saiddielectric material is deposited by MOCVD.
 154. The structure accordingto claim 141 wherein said dielectric material is deposited by CVD. 155.The structure according to claim 141 wherein said electrode materialcomprises a noble metal material.
 156. The structure according to claim141 wherein said microstructures have a constant thickness incross-section.
 157. The structure according to claim 141 wherein saidmicrostructures have a “T” shaped cross-section.
 158. The structureaccording to claim 141 wherein said microstructures have one ofincreasing and decreasing cross-section.
 159. The structure according toclaim 141 wherein said dielectric material comprises a material having adielectric constant of at least
 50. 160. The structure according toclaim 141 wherein each one of said microstructures, and dielectric andelectrode materials, forms an individual capacitor.
 161. The structureaccording to claim 141 wherein said microstructures, and dielectric andelectrode materials, form a single capacitor.